Digital integrated circuit devices often employ special circuits to aid testability so as to make the operation of testing a digital device simpler, more efficient and more effective.
A very common built-in test circuit is a scan path or chain by which the bistable elements (flip-flops and/or latches) within a digital device are connected into a shift register called a scan path or scan chain. With the digital device in scan mode, an input pattern is serially scanned into the bistable elements (i.e., serially shifted into the bistable elements). The digital device is then operated in the normal mode for one clock period, which causes the bistable element contents to act as inputs to the internal combinatorial logic, and causes subsequent response values to be stored in the bistable elements. The digital device is again placed in the scan mode to allow the response pattern stored in the bistable elements to be serially scanned out (i.e., serially shifted out) and compared with the correct response.
In the scan mode, input patterns are provided by external test equipment which also receives the response patterns shifted out of the storage elements of a scan path. Typically, the input patterns and response patterns are communicated over a common serial test bus, as for example specified by the IEEE Standard 1149.1 for a Standard Test Access Port. Often the serial scanning by the external test equipment must be performed at a test clock frequency that is different from and/or asynchronous relative to the system clock frequency at which the device under test performs its operational functions. Also, the test clock could be discontinuous.
As a result of these characteristics of the test clock frequency of test equipment, ASICs typically do not use dynamic logic, which is characterized by the need to be continuously refreshed, for example by receipt of a clock pulse at a minimum specified rate, in order to maintain data stored in memory. The advantage of dynamic logic include smaller size, lower power, and higher speed performance as compared to static logic (in which the last memory state is held indefinitely long in the absence of a clock).
U.S. Pat. No. 5,181,191, W.D. Farwell, describes a technique for testing integrated circuits (ICs) at higher clock speeds than the clock speed provided by test equipment. This supports a known technique for testing dynamic logic of ensuring that the chip clock meet a maximum clock-to-clock period. However, this technique requires that the test clock and chip clock be synchronously related, and cannot be done at all for some forms of external test equipment.
There is accordingly a need for a scan test circuit that employs a continuous system clock and a test clock that can be discontinuous and/or asynchronous.